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NX2423
TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH INTEGRATED FET DRIVER, DIFFERENTIAL CURRENT SENSE & 5V BIAS REGULATOR
PRELIMINARY DATA SHEET Pb Free Product The NX2423 is a two-phase PWM controller with inte- n Differential inductor DCR sensing eliminates the problem with layout parasitic grated FET driver designed for low voltage high current n 5V bias regulator available application. The two phase synchronous buck converter offers ripple cancelation for both input and output. The n Low Impedance On-board Drivers NX2423 uses differential remote sensing using either cur- n Hiccup current limit and IOUT indication rent sense resistor or inductor DCR sensing to achieve n Power Good for power sequencing accurate current matching between the two channels. n EN2_B pin allows the slave channel on and off while the master channel is working Differential sensing eliminates the error caused by PCB n Programmable frequency board trace resistance that otherwise presents when usn Prebias start up ing a single ended voltage sensing. In addition the NX2423 offers high drive current capabil- n OVP without negative spike at output ity especially for keeping the synchronous MOSFET off n Selectable between internal and external reference during SW node transition, can provide regulated 5V to n Internal Schottky diode from PVCC to BST IC biasing and drivers via 5V bias regulator, allows the n Pb-free and RoHS compliant slave channel on and off via EN2_B pin while the main channel is working. Other features: PGOOD output, pro- n Graphic card High Current Vcore Supply grammable switching frequency and hiccup current lim- n High Current on board DC to DC converter iting circuitry. applications
12V BUS
R10
2N3904
DESCRIPTION
FEATURES
APPLICATIONS
TYPICAL APPLICATION
C11 C10
VCCDRV
2N3904
BST1 C12 HDRV1 SW1 Q1 L1
5V
R13 R14
VOUT
C13 Q2 R29 C15 C14
C31 R11 C30
PVCC
LDRV1
5VCC REFIN AGND CSCOMP
R16 R17 C28 CS+1 R28
NX2423
CS-1
R15
C29
C17 BST2 C19 HDRV2 SW2 Q3
C18
RT IOUT/IMAX
C27 R18 C26
L2 R27 C20 C21
VCOMP
R19 C25 LDRV2 Q4
C22
FB
R20
EN2_B
CS+2 CS-2 R24
R26
VOUT
PGND(PAD)
INREFOUT/POK
C24
Ref for external circuitry
Figure1 - Typical application of NX2423
ORDERING INFORMATION
Device NX2423CMTR
Rev. 2.1 12/01/08
Temperature 0 to 70oC
Package MLPQ 4x4 - 24L
Frequency 50kHz to 1MHz
Pb-Free Yes 1
NX2423
ABSOLUTE MAXIMUM RATINGS
Vcc to PGND & BST to SW voltage .................... -0.3V to 6.5V BST to PGND Voltage ...................................... -0.3V to 35V SW to PGND .................................................... -2V to 35V All other pins .................................................... -0.3V to 6.5V Storage Temperature Range ............................... -65oC To 150oC Operating Junction Temperature Range ............... -40oC To 125oC Lead temperature(Soldering 5s) ........................... 260oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
24 LEAD PLASTIC MLPQ
VCCDRV LDRV1 PVCC LDRV2
SW1
24 23 22 21 20 19 HDRV1 BST1 5VCC AGND EN2_B CS+1 1 2 3 4 5 6 7 CS-1 8 CS-2 9 CS+2 10 11 12 IOUT/IMAX VCOMP RT PGND(PAD) 18 17 HDRV2 BST2
SW2
JA 30.5o C/W
16 INREFOUT/POK 15 REFIN
14 CSCOMP 13 FB
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over 5Vcc = 5V, PVcc= 5V, VBST-VSW =5V, EN2_B=GND, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETER Supply Voltage(Vcc) 5VCC ,PVCC Voltage Range 5VCC Supply Current (static) PVCC Supply Current (Dynamic) VBST Voltage Range VBST Supply Current ((Dynamic))
Rev. 2.1 12/01/08
SYM VCC
TEST CONDITION
MIN 4.5 -
TYP 5 6.7 4.4
MAX 5.5
UNITS V mA mA
ICC (Static) REFIN=GND, EN2_B=5V REFIN=5V, EN2_B=GND, ICC Freq=200Khz per phase (Dynamic) CLOAD=2200PF VBST to VSW REFIN=5V, EN2_B=GND, VBST Freq=200Khz per phase (Dynamic) CLOAD=2200PF
4.5
5 4.5
5.5
V mA
2
NX2423
PARAMETER Under Voltage, Vcc & EN2_B VCC-Threshold VCC-Hysteresis EN2_B Threshold EN2_B Hysteresis Reference Voltage Ref Voltage Ref Voltage line regulation Oscillator (Rt) Frequency for each phase Ramp-Amplitude Voltage Ramp Peak Ramp Valley Max Duty Cycle Min Duty Cycle Transconductance Amplifiers(CSCOMP) Open Loop Gain Transconductance Voltage Mode Error Amplifier Gain Open Loop Input Offset Voltage Output Current Source Output Current Sink Output HI Voltage Output LOW Voltage SS (Internal ) Soft Start time POK/INFEROUT Threshold Hysteresis POK Voltage High Side Driver (CL=4700pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (CL=10000pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current
Rev. 2.1 12/01/08
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
VCC_UVLO VCC_Hyst
VCC Rising VEN2_B Rising
4.1 0.4 0.82 80 0.6 0.2
V V V mV V % KHz V V V % %
VREF
4.5V<5Vcc<5.5V
Fs VRAMP
Rt=100kohm
400 1.02 2.2 1.18 97 0
200Khz/Phase
50
65 1600
dB umoh dB mV mA mA V V mS %VP % V
50 Vio_v 5 5 Vcc-1.5 0.5 Tss 400Khz/Phase VFB Rising IOUT=5mA(sourcing) 1.191 2.5 73 5 1.215 0
1.24
Rsource(Hdrv) Rsink(Hdrv)
I=200mA I=200mA
1 0.7 19 18.5 40
ohm ohm ns ns ns
THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10%-10%
Rsource(Ldrv) Rsink(Ldrv)
I=200mA I=200mA
1 0.5
ohm ohm
3
NX2423
PARAMETER Supply Voltage(Vcc) Rise Time Fall Time Deadband Time Propagation Delay Current Sense Amplifier(CS+, CS-) Input Offset Voltage Voltage Gain OVP Threshold OVP Threshold FB UVLO Threshold FB UVLO Threshold REFIN VOLTAGE REFIN Voltage Range Disable Voltage Threshold Threshold Enable Internal Reference 5V AUX REG Regout Output Voltage High Regout Output Voltage Low SYM TEST CONDITION TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% Tdealy(H) IN going High to Ldrv going Low MIN TYP 34 18 10 14 MAX UNITS ns ns ns ns
-2 29.7 percent of Vp percent of Vp 0.4 0.3
30 130 70
2 30.3
mV V/V % %
0.35 75
2.5 0.4
V V %VCC
VIN=12V, PVCC=3V VIN=12V, PVCC=5.8V, VCCDRV connected to 12V by 1k resistor forward current=10mA
11 2
V V
Internal Schottky Diode Forward voltage drop
600
mV
Rev. 2.1 12/01/08
4
NX2423
PIN DESCRIPTIONS
SYMBOL HDRV1 BST1 5VCC PIN DESCRIPTION High side gate driver for Channel 1. Bootstrap supply for Channel 1. IC's supply voltage. This pin biases the internal logic circuits. A minimum 1uF ceramic capacitor is recommended to connect from this pin to ground plane. Controller analog ground pin. This pin is used to startup or shutdown the channel2 only while 5VCC and REFIN is ready. For two phase opeartion, EN2_B is preferred to be tied to GND. For one phase opeartion, EN2_B is preferred to be tied to 5VCC. During the operation, it is not recommended to change EN2_B voltage. Positive input of the channel 1 differential current sense amplifiers. It is connected directly to the RC junction of the respective phase's output inductor. Negative input of the channel 1 differential current sense amplifiers. It is connected directly to the negative side of the respective phase's output inductor. Negative input of the channel 2 differential current sense amplifiers. It is connected directly to the negative side of the respective phase's output inductor. Positive input of the channel 2 differential current sense amplifiers. It is connected directly to the RC junction of the respective phase's output inductor. This pin indicates average output current level and sets OCP threshold using a resistor from this pin to ground. A no more than 1nF ceramic capacitor is recommended to connect this pin to ground plane to filter the noise on this pin. This pin programs the internal oscillator frequency using a resistor from this pin to ground. This is the output pin of the error amplifier. This pin is the error amplifier inverting input. It is connected to the output voltage via a voltage divider. The output of the transconductance op amp for current balance circuit. An external RC is connected from this pin to GND to stabilize the current loop. External reference input. If pull-up to >4.5V, internal reference is used. If driven by an external voltage ranged from 0.4V to 2.5V, external reference is used with slew rate following SS rate. If REFIN is below 0.4V, device is disabled. This pin has dual functions. When FB pin is below 75% of internal 0.6V reference, this pin is held low. When FB reaches above this threshold, this pin is tied to an internal 1.25V reference, allowing it to be used as a reference for any external op amp circuitry as well as an indicator of power OK. This pin can not be connected directly to an output capacitor. An RC network is needed which also provides a slow ramp up of the reference for the external op amp. 5
AGND EN2_B
CS+1
CS-1
CS-2
CS+2
IOUT/IMAX
RT
VCOMP FB
CSCOMP
REFIN
INREFOUT/ POK
Rev. 2.1 12/01/08
NX2423
SYMBOL BST2 HDRV2 SW2 LDRV2 PVCC PIN DESCRIPTION Bootstrap supply for Channel 2. High side gate driver for Channel 2. Switch node for Channel2. Low side gate driver for Channel 2. This pin provide the supply voltage for the lower MOSFET drivers. This pin provide the supply voltage for the lower MOSFET drivers. A high frequency ceramic 1uF must be placed close to this pin and tied to PGND to provide peak current needed for low side MOSFETs. Low side gate driver for Channel 1. Switch node for Channel 1. This is the ground connection for the power stage of the controller. The output of the 5V regulator controller that drives a low current low cost exterVCCDRV nal BIPOLAR transistor or an external MOSFET to regulate the voltage at Vcc pin derived from BUS voltage. A resistor with value from 1k to 10k is used to connect VCCDRV and VBUS. Pulling down VCCDRV is used to disable chip in NX2423 application .
LDRV1 SW1 PGND
Rev. 2.1 12/01/08
6
NX2423
BLOCK DIAGRAM
+12V
VCCDRV
1.25V
OFF ON
5VCC
+5V
EN2_B
ON OFF
Bias generator
0.6V 1.6V 1.25V
PVCC UVLO UVLO
OVP
+5V +12V
BST1 DrvH1 SW1 FET driver
ENBUS_2
+5V
0.82/0.74
0.35 /0.3V
ENBUS_2 Hiccup
start
VOUT +1.2V/50A
DAC
REFIN
FILTER 0.6V
DrvL1 PGND
VOUT
3.6 /3.3V
Vp Digital start SS_finish Dis_EA SW2 BST2 DrvH2
FB VCOMP ramp1 Two phase OSC set2 Rt
Vp*130% FILTER
OVP
R S
Set1 K=30
Q
DrvL2
KR V1.25 R KR CS+1 CS-1 R PWM control logic and driver KR V1.25 R CS+2 CS-2
CS01 CS02
ramp2
FB
R KR Slave channel control Hiccup Hiccup Logic V1.25 gm=0.04A/V IOUT/IMAX CScomp(SS/EN)
Vp*75%
SS_finished
/ 2
6 Cycles filter
INREFOUT/POK
1.25V
1.25V
SS_FINISHED
AGND
Vp*70%
FB
Figure 2 - Block diagram of NX2423
Rev. 2.1 12/01/08
7
NX2423
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN VOUT IOUT FS - Input voltage - Output voltage - Output current - Operation frequency for each channel
L OUT =0.54uH
Choose inductor from Vishay IHLP_5050FD-01 with L=0.68uH DCR=1.4m. Current Ripple is recalculated as
DVRIPPLE - Output voltage ripple DIRIPPLE - Inductor current ripple
IRIPPLE = =
VIN -VOUT VOUT 1 x x LOUT VIN FS
...(2) 12V-1.2V 1.2V 1 x x = 3.97A 0.68uH 12V 400kHz
Design Example
The following is typical application for NX2423. VIN = 12V VOUT=1.2V IOUT=50A IOUT_max=60A DVRIPPLE <=12mV DVDROOP<=120mV @30A step FS=400kHz Phase number N=2
Output Capacitor Selection
Output capacitor value is basically decided by the output voltage ripple, capacitor RMS current rating and load transient. Based on Voltage Ripple For electrolytic, POSCAP bulk capacitor, the ESR (equivalent series resistance) and inductor current typically determines the output voltage ripple.
ESRdesire =
VRIPPLE 12mV = = 3.022m IRIPPLE 3.97A
...(3)
If low ESR is required, for most applications, mul-
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
tiple capacitors in parallel are better than a big capacitor. For example, for 12mV output ripple, SANYO OSCON capacitors 2R5SEPC1000MX(1000uF 7m) are chosen.
N=
E S R E x IR I P P L E VR IPPLE
...(4)
Number of Capacitor is calculated as
L OUT =
VIN -VOUT VOUT 1 x x IRIPPLE VIN FS IOUTPUT N
...(1)
7m x 3.97A 12mV N =2.3 For ceramic capacitor, the current ripple is determined by the number of capacitor instead of ESR N=
COUT = IRIPPLE 8 x FS x VRIPPLE
...(5)
IRIPPLE =k x
where k is between 0.2 to 0.4. Select k=0.2, then
12V-1.2V 1.2V 1 L OUT = x x 50A 12V 400kHz 0.2 x 2
Typically, the calculated capacitance is so small that the output voltage droop during the transient can not meet the spec although ripple is small.
Rev. 2.1 12/01/08
8
NX2423
Based On Transient Requirement Typically, the output voltage droop during transient is specified as:
VDROOP ...(6)
0 if LEFF Lcrit = LEFF x Istep - ESR E x CE V OUT
if LEFF Lcrit
...(10)
For example, assume voltage droop during transient is 120mV for 30A load step. If the OS-CON capacitors (1000uF, 7m ) is used, the critical inductance is given as
Lcrit =
ESR E x C E x VOUT = Istep
7m x 1000F x 1.2V = 0.28H 30A
The effective inductor value is 0.34uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
where is the a function of capacitor, etc.
0 if LEFF Lcrit = LEFF xIstep - ESR x COUT V OUT
where
if LEFF Lcrit
...(7)
number of capacitors is
= =
...(8)
LEFF x Istep VOUT
- ESR E x CE
L EFF = L crit
LOUT 0.68uH = = 0.34uH N 2 ESR x COUT x VOUT ESR E x C E x VOUT = = Istep Istep
0.34H x 30A - 7m x 1000F = 1.5us 1.2V
ESR E xIstep Vtran + VOUT x2 2 x LEFF x CE xVtran
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
N= =
7mx 30A + 120mV 1.2V x (1.5us)2 2 x 0.34Hx1000F x120mV = 1.78
The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2. It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. 9
...(9)
where
Rev. 2.1 12/01/08
NX2423
Control Loop Compensator Design
NX2423 can control and drive two channel synchro-
Gain= Fz =
nous bucks wih 180o phase shift between each other. t
One of two channels is called master, the other is called slave. They are connected together by sharing the same output capacitors. Voltage loop is designed to regulate output voltage. In order to achieve the current balance in these two synchronous buck converters, current loop compensation network is employed to to make sure the currents in slave is following the master.
R3 R2
... (11) ... (12) ... (13)
1 2 x x R3 x C1 1 2 x x R 3 x C2
Fp
C2 Vout R2 Fb Ve R1 Vref R3 C1
Voltage Loop Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response,compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crosstors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. ing 0dB with -20dB/decade. Power stage output capaci-
Figure 3 - Type II compensator
power stage Gain(db) 40dB/decade loop gain 20dB/decade
A. Type II compensator design If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. Type II compensator can be realized by simple RC circuit without feedback as shown in figure 3. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain. For this type of compensator, FO has to satisfy FLCRev. 2.1 12/01/08
compensator Gain
FZ FLC FESR FO FP
Figure 4 - Bode plot of Type II compensator
10
NX2423
two 1.5uH inductors. 1.Calculate the location of LC double pole F LC and ESR zero FESR. B. Type III compensator design For low ESR output capacitors, typically such as Sanyo OSCON and POSCAP, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. In design example, six electrolytic capacitors are used as output capacitors. The system is compensated with type III compensator. The following figures and equations show how to realize the this type III compensator with electrolytic capacitors.
FLC = =
1 2 xx LEFF x COUT 1
2 xx 0.75uHx10800uF = 1.768kHz
FESR = =
1 2 x x ESR x COUT
1 2 x x 13m x 1800uF = 6.801kHz
2.Set R2 equal to10k and calculate R1.
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 C x C2 2 x x R4 x 1 C1 + C2
...(14) ...(15) ...(16) ...(17)
R1=
R 2 x VREF 10k x 0.6V = = 10k VOUT -VREF 1.2V-0.6V
3. Set crossover frequency FO=15kHz. 4.Calculate R3 value by the following equation.
R3=
V O S C 2 x x FO x L E F F x x R2 V in ESR
1V 2 x x 15kHz x 0.75uH = x x 10k 12V 2.16m =27.3k
Choose R 3 =27.4k. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole.
C1= 1 2 x x R3 x Fz
where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator.
Zin R3
Vout
Zf C1 C2 R4
R2 C3 R1
Fb Ve Vref
1 = 2 x x 27.4kx 0.75 x 1.768kHz =4.4nF
Choose C1=4.7nF. 6. Calculate C 2 by setting compensator pole Fp at half the swithing frequency.
C2= = 1 x R 3 x Fs
Figure 5 - Type III compensator
1 x 2 7 .4k x 4 0 0 k H z =30pF
Choose C2=33pF.
Rev. 2.1 12/01/08
11
NX2423
R1=
Gain(db)
power stage FLC
40dB/decade
R 2 x VREF 10k x 0.6V = = 10k VOUT -VREF 1.2V-0.6V
Choose R1=10k. 3. Calculate C3 by setting FZ2 = FLC and Fp1 =FESR.
loop gain
FESR
C3 = =
20dB/decade
1 1 1 x( ) 2 x x R2 Fz2 Fp1
1 1 1 x( ) 2 x x 10k 6.1kHz 22.7kHz =1.9nF
Choose C3=1.8nF. 5. Calculate R 3 by equation (13).
compensator
R3 =
FZ1 FZ2 FP1 FO FP2
1 2 x x FP1 x C3
1 2 x x 22.7kHz x 1.8nF = 3.89k =
Choose R3=3.92k. 6. Calculate R4 by choosing FO=40kHz. R4 = = VOSC 2 x x FO x LEFF R2 x R3 x x Vin ESR R 2 + R3
Figure 6 - Bode plot of Type III compensator The transfer function of type III compensator is given by:
(1+ sR4 x C2 ) x [1+ s(R2 + R3 ) x C3 ] Ve 1 = x VOUT sR2 x (C2 + C1) (1+ sR x C2 x C1 ) x 1+ sR x C ( 4 3 3) C2 + C1
Use the same power stage requirement as demo board. The crossover frequency has to be selected as FLC1V 2 x x 40kHz x 0.34uH 10k x 3.92k x x 12V 3.5m 10k + 3.92k =5.73k Choose R4=5.62k. 7. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
C2 = =
1 2 x x FZ1 x R 4
FLC = =
1 2 x x LEFF x COUT 1
1 2 x x 0.75 x 6.1kHz x 5.62k = 6.2nF
2 x x 0.34uH x 2000uF = 6.1kHz
Choose C2=6.8nF. 8. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency.
FESR = =
1 2 x x ESR x COUT
C1 = =
1 2 x x 3.5m x 2000uF = 22.7kHz
2.Set R2 equal to10k.
Rev. 2.1 12/01/08
1 2 x x R 4 x FP2
1 2 x x 5.62k x 200kHz = 141pF
Choose C1=150pF. 12
NX2423
Current Loop Compensator Design
Power stage Master channel Compensation D(s) 1 Vosc d Vin s*L+Req iL
Current Sensing Amplifier Gain
s*L+DCR Rs*Cs*s+1 Inductor Current sense
Figure 7 - Current loop control diagram
VIN
master channel DCR L
Vbias
Rs Rs VIN PWM control logic and driver
Cs VOUT
Slave channel 1 DCR L
Ramp for slave channel Vbias
Rs Rs CSCOMP Rcc C1
Cs
Slave channel control C2 Slave channel control Slave channel
Figure 8 - Function diagram of current loop
Rev. 2.1 12/01/08
13
NX2423
Inductor Current Sensing
VIN iL Control & Driver L DCR VOUT Rs Current Sensing Amplifier Cs VS_IL
racy during the transient if droop function is required. The illustration is shown in the following figure.
VS_IL----Voltage accross the sensing capacitor Cs iL--- inductor current
Overshoot caused by inductor nonlinearity
Rs
Figure 9 - Inductor current sensing using RC network. The inductor current can be sensed through a RC network as shown above. The advantage of the RC network is the lossless comparing with a resistor in series with output inductor. The selection of the resistor sensing network is chosen by the following equation:
R S x CS = L DCR
Droop misbehavoir caused by overshoot of VS_IL Output voltage with droop function
...(18)
Figure 10 - Droop accuracy affected by the nonlinearity of inductor. In this case, the sensing resistor has to be chosen
If the above equation is satisfied, the voltage across the sensing capacitor Cs will be equal to the inductor current times DCR of inductor for all frequency domain.
VS _ IL = DCR x iL
RS
L DCR x CS
to compensate the overshoot. This selection only affects the small signal mode of current loop. For DC accuracy, there is no effect since the DC voltage across the sensing capacitor will equal to the DCR times inductor current at DC load no matter what Rs is. In this example, Rs=620. RS value is preferred to be less than 400 in NX2423's application, therefore we need to reiterate the calculation, choose CS 2.2uF instead. RS value is finally chosen as 301 . Powe dissipation of Rs resistor is calculated as followed:
If the sensing capacitor is chosen
CS = 1F CS must be X7R or COG ceramic capacitor. The sensing resistor is calculated as RS = L DCR x CS
For example, for 0.68uH inductor with 1.4m DCR, we have
RS =
0.68H = 486 1.4m x 1F
In most of cases, the selection of sensing resistor based on the above equation will be sufficient. However, for some inductor such as toroid coiled inductor with micrometal, even the product of sensing resistor and capacitor is perfectly match with L/DCR, the voltage across the capacitor still has overshoot due to the nonlinearity of inductor. This will affect the droop accu-
PD (RS ) = =
(VIN - VOUT )2 V2 x D + OUT x (1 - D) RS RS
(12 V - 1.2V)2 (1.2 V)2 x 0. 1 + x (1 - 0.1) 301 301 = 0.04 W
The power rating of Rs should be over 0.04W.
Rev. 2.1 12/01/08
14
NX2423
Current Loop Compensation
FP1 =
Slave channel power stage
Req 2x xL
=
7.4m = 1.7kHz 2 x x 0.68H
The current compensation transfer function is
-20 dB
given as
D(s) = gm x s x ( C1 + C2 ) 1 + s x Rcc x C1 R x C1 x C2 1 + s x cc C1 + C2
Current loop compensation
It has one zero and one pole. The ideal is to
Loop gain for slave channel -20dB 0 DB -40dB Fzc Fo Fpc
choose resistor Rcc to achieve desired loop gain such as 50kHz. Rcc can be calculated as
Fp1
Rcc =
where
2 x x Fo x L x Vosc gm x VIN x K C x DCR 60 k = 22.9 2k+ RS
...(19)
Figure 11 - Bode plot of current loop The diagram and bode plot for current loop of NX2423 is shown in above figure. The current signal through inductor sensing is amplified by current sensing differential amplifier. The amplified slave current signal is compared with the amplified inductor current from master channel (channel 1 for NX2423) through a transconductance amplifier, the difference between channel current will change the output of transconductance amplifier, which will compare with a internal ramp signal and changes the duty cycle of slave channel buck converter. If the inductor are perfectly matched and the PWM controller has no offset, the DC current in slave channel will equal to the DC current of master channel (channel 1) due to the gain of current loop. From the bode plot, the power stage has one pole located at
KC
60k and 2k is the internal resistance for the current sensing amplifier. For fast response, we can set the current loop cross-over frequency one and half times of voltage loop cross-over frequency. Since the voltage loop cross-over frequency is typically selected as 1/10 of switching frequency, we choose FO=50kHz.
Rcc = 2 x x 50kHz x 0.68H x 1V = 442 1.6mA / V x 12 V x 22.9 x1.4m
Select
Rcc = 430 .
The selection of capacitor C1 is such that the zero of compensation will cancel the pole of power stage, therefore,
C1 = L 0.68H = = 214nF Req x Rcc 7.4m x 430
2xxL where Req is the equivalent resistor and it is given by
R eq DCR + R dson _ con x VOUT V + Rdson _ syn x 1 - OUT VIN VIN
FP1 =
Req
Typically, the capacitor C1 is so big that the current loop may start slowly during the start up. Therefore, smaller capacitor can be selected. However, the selected capacitor can not reduce too much to cause phase droop. Select C1=220nF. The capacitor C2 is an option and it is used to filter out the switching noise. C2 can be calculated as
R dson _ con is the Rdson of control FET and R dson _ syn is
the Rdson of synchronous FET. For this example,
Req = 7.4m
The pole is located as
Rev. 2.1 12/01/08
15
NX2423
C2 = 1 1 = = 1.85nF x Rcc x FS x 430 x 400kHz
0.2*Iout=0.2*50A=10A. A combination of ceramic and electrolytic(SANYO WG or WF series) or OSCON type capacitors can achieve both ripple current capability together with having enough capacitance such that input voltage will not sag too much. In this application, one OSCON SVPC180M(180uF, 16V, 2.8A) and three 10uF X5R ceramic capacitors are selected. A 1uH input inductor is recommended to slow down ...(20) the input current transient. Suppose power stage efficiency is 0.8, then input current can estimated by
Select C2=2.2nF.
Frequency Selection
The frequency can be set by external Rt resistor. The relationship between frequency per phase and RT pin around 400kHz is shown as follows.
RT
40000000 FS
Frequency(kH v R o m z) s t(k h )
IINPUT =
IO U T x VOUT 60 A x 1 . 2 V = = 7 .5 A x VIN 0 . 8 x 12 V
10 20 10 00 Frequency(kHz) 80 0
In this application, Coilcraft DO3316P_102HC with RMS rating 10A is chosen.
0.5
60 0 40 0 20 0 0 0 5 0 10 0 10 5 R om t(k h ) 20 0 20 5 300
0.4
Singlephase Two phase
I RMS (IN ) 0.3 Iout
0.2 0.1 0
Figure 12 - Frequency vs Rt chart
Three phase
0 0.1 0.2 D 0.3 0.4 0.5
Input Filter Selection
The selection criteria of input capacitor are voltage rating and the RMS current rating. For conservative consideration, the capacitor voltage rating should be 1.5 times higher than the maximum input voltage. The RMS current rating of the input capacitor for multi-phase converter can be estimated from the above Figure 13. First, determine the duty cycle of the converter (VO/ VIN). The ratio of input RMS current over output current can be obtained. Then the total input RMS current can be calculated. From this figure, it is obvious that a multiphase converter can have a much smaller input RMS current, which results in a lower amount of input capacitors that are required. For example, Vin=12V, Vout=1.2V. The duty cycle is D=Vout/Vin=1.2/12=10%. From the figure, for two phase,
Rev. 2.1 12/01/08
Figure 13 - Normalized input RMS current vs. duty cycle
Over Current/Short Circuit Protection
The converter will go into hiccup mode if the output current reaches a programmed limit I OCP determined by the resistor value Rocp at pin IOUT/IMAX.
ROCP =
2k + RS 1.25V 2 1 x x x 0.04mA / V 60k DCR IOCP
...(21)
Where Iocp is the desired over current protection level, R S is the current sensing matching resistor when using DCR sensing method.
the
normlized
RMS
current
is 16
NX2423
Over Voltage Protection
Over voltage protection is achieved by sensing the output voltage through resistor divider. The sensed voltage on FB pin is compared with 130%*VREF to generate the OVP signal.
TSW is the sum of TR and TF which can be found in
mosfet datasheet, IOUT is output current, and FS is switching frequency. Swithing loss PSW is frequency dependent.
Soft Start and Enable Signal Operation Power MOSFETs Selection
The NX2423 requires two N-Channel power MOSFETs for each channels. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, eight NTD60N02 are used. They have the following parameters: VDS=25V, ID =62A,RDSON =12m,QGATE =9nC. There are three factors causing the MOSFET power loss:conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as:
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
The NX2423's master channel will start operation after 5VCC and REFIN have reached their threshold voltages. Pulling down VCCDRV will cause 5VCC drop below to its threshold, then shuts down NX2423. The slave channel will start operation only when EN2_B is less than 0.8V, 5VCC and REFIN have reached their respective thresholds. For two phase opeartion, EN2_B is preferred to be tied to GND. For one phase opeartion, EN2_B is preferred to be tied to 5VCC. During the operation, it is not recommended to change EN2_B voltage. Once the converter starts, there is a soft start sequence of 1024 steps between 0 and VREF. The ramp rate is determined by the switching frequency.
dVO VO = dt 1024 x TS
...(25)
...(22) where QHGATE is the high side MOSFETs gate
Layout Considerations
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET,
charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device. Conduction loss is simply defined as:
PHCON =IOUT 2 x D x RDS(ON) x K PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON
...(23)
inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to
Where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency and should be selected for the worst case. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. 1 PSW = x VIN x IOUT x TSW x FS 2
Rev. 2.1 12/01/08
...(24)
reduce the EMI radiated by the power loop due to the 17
NX2423
high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. 12. Inductor current sense line should be connected directly to the inductor solder pad.
Rev. 2.1 12/01/08
18
NX2423
MLPQ 24 PIN 4 x 4 PACKAGE OUTLINE DIMENSIONS
NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
Rev. 2.1 12/01/08
19
NX2423
MLPQ 24 PIN 4 x 4 TAPE AND REEL INFORMATION
NOTE: 1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL. 2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
Rev. 2.1 12/01/08
20

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